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Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7.

M. Gupta, P. Weckx, S. Cosemans, P. Schuddinck, R. Baert, D. Yakimets, D. Jang, Y. Sherazi, P. Raghavan, A. Spessot, A. Mocuta, and W. Dehaene. ESSDERC, page 256-259. IEEE, (2017)

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Pieter Zwieten

Pieter Wolter

Pieter Ploumen

Pieter Dingeldey

Pieter Steenhuis

Other publications of authors with the same name

PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology.S. Yang, P. Schuddinck, M. Bardon, Y. Xiang, A. Veloso, B. Chan, G. Mirabelli, G. Hiblot, G. Hellings, and J. Ryckaert. VLSI Technology and Circuits, page 1-2. IEEE, (2023)Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node.R. Chen, G. Sisto, M. Stucchi, A. Jourdain, K. Miyaguchi, P. Schuddinck, P. Woeltgens, H. Lin, N. Kakarla, A. Veloso and 7 other author(s). VLSI Technology and Circuits, page 429-430. IEEE, (2022)Dedicated technology threshold voltage tuning for 6T SRAM beyond N7.M. Gupta, P. Weckx, S. Cosemans, P. Schuddinck, R. Baert, D. Jang, Y. Sherazi, P. Raghavan, A. Spessot, A. Mocuta and 1 other author(s). ICICDT, page 1-4. IEEE, (2017)Design enablement of CFET devices for sub-2nm CMOS nodes.O. Zografos, B. Chehab, P. Schuddinck, G. Mirabelli, N. Kakarla, Y. Xiang, P. Weckx, and J. Ryckaert. DATE, page 29-33. IEEE, (2022)Self-Heating in iN8-iN2 CMOS Logic Cells: Thermal Impact of Architecture (FinFET, Nanosheet, Forksheet and CFET) and Scaling Boosters.B. Vermeersch, E. Bury, Y. Xiang, P. Schuddinck, K. Bhuwalka, G. Hellings, and J. Ryckaert. VLSI Technology and Circuits, page 371-372. IEEE, (2022)Memories for NTC.T. Gemmeke, M. Sabry, J. Stuijt, P. Schuddinck, P. Raghavan, and F. Catthoor. Near Threshold Computing, Springer, (2016)PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch.P. Schuddinck, F. Bufler, Y. Xiang, A. Farokhnejad, G. Mirabelli, A. Vandooren, B. Chehab, A. Gupta, C. Neve, G. Hellings and 1 other author(s). VLSI Technology and Circuits, page 365-366. IEEE, (2022)Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7.M. Gupta, P. Weckx, S. Cosemans, P. Schuddinck, R. Baert, D. Yakimets, D. Jang, Y. Sherazi, P. Raghavan, A. Spessot and 2 other author(s). ESSDERC, page 256-259. IEEE, (2017)Design Technology co-optimization for N10.J. Ryckaert, P. Raghavan, R. Baert, M. Bardon, M. Dusa, A. Mallik, S. Sakhare, B. Vandewalle, P. Wambacq, B. Chava and 18 other author(s). CICC, page 1-8. IEEE, (2014)

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Disambiguation of "Schuddinck, Pieter"

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Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7.

Please choose a person to relate this publication to

Pieter Zwieten

Pieter Wolter

Pieter Ploumen

Pieter Dingeldey

Pieter Steenhuis

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Schuddinck, Pieter"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7.

Please choose a person to relate this publication to

Pieter Zwieten

Pieter Wolter

Pieter Ploumen

Pieter Dingeldey

Pieter Steenhuis

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7.