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Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7.

M. Gupta, P. Weckx, S. Cosemans, P. Schuddinck, R. Baert, D. Yakimets, D. Jang, Y. Sherazi, P. Raghavan, A. Spessot, A. Mocuta, and W. Dehaene. ESSDERC, page 256-259. IEEE, (2017)

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Dmitry Sveshnikov

Dmitry Ivanov

Dmitry Lobaskin

Dmitry Shvedov

Dmitry Suslov

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Holisitic device exploration for 7nm node.P. Raghavan, M. Bardon, D. Jang, P. Schuddinck, D. Yakimets, J. Ryckaert, A. Mercha, N. Horiguchi, N. Collaert, A. Mocuta and 5 other author(s). CICC, page 1-5. IEEE, (2015)Dimensioning for power and performance under 10nm: The limits of FinFETs scaling.M. Bardon, P. Schuddinck, P. Raghavan, D. Jang, D. Yakimets, A. Mercha, D. Verkest, and A. Thean. ICICDT, page 1-4. IEEE, (2015)Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.T. Bao, D. Yakimets, J. Ryckaert, I. Ciofi, R. Baert, A. Veloso, J. Bömmels, N. Collaert, P. Roussel, S. Demuynck and 6 other author(s). ESSDERC, page 102-105. IEEE, (2014)Lateral NWFET optimization for beyond 7nm nodes.D. Yakimets, D. Jang, P. Raghavan, G. Eneman, H. Mertens, P. Schuddinck, A. Mallik, M. Bardon, N. Collaert, A. Mercha and 3 other author(s). ICICDT, page 1-4. IEEE, (2015)Device/system performance modeling of stacked lateral NWFET logic.V. Huang, C. Pan, D. Yakimets, P. Raghavan, and A. Naeemi. ISQED, page 215-220. IEEE, (2016)Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7.M. Gupta, P. Weckx, S. Cosemans, P. Schuddinck, R. Baert, D. Yakimets, D. Jang, Y. Sherazi, P. Raghavan, A. Spessot and 2 other author(s). ESSDERC, page 256-259. IEEE, (2017)Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM.T. Bao, S. Sakhare, J. Ryckaert, D. Yakimets, A. Mercha, D. Verkest, A. Thean, and P. Wambacq. ICICDT, page 1-4. IEEE, (2015)STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process.D. Jang, M. Bardon, D. Yakimets, K. Miyaguchi, A. Keersgieter, T. Chiarella, R. Ritzenthaler, M. Dehan, and A. Mercha. ESSDERC, page 159-162. IEEE, (2013)

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Disambiguation of "Yakimets, Dmitry"

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Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7.

Please choose a person to relate this publication to

Dmitry Sveshnikov

Dmitry Ivanov

Dmitry Lobaskin

Dmitry Shvedov

Dmitry Suslov

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Yakimets, Dmitry"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7.

Please choose a person to relate this publication to

Dmitry Sveshnikov

Dmitry Ivanov

Dmitry Lobaskin

Dmitry Shvedov

Dmitry Suslov

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7.