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Disambiguation of "Lewis, Dean L."

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A scanisland based design enabling prebond testability in die-stacked microprocessors.

, and . ITC, page 1-8. IEEE Computer Society, (2007)

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J. D. Lewis-Williams

Ingrid Lewis

Catharine Janna Lewis

Howard Lewis

Ian Lewis

 

Other publications of authors with the same name

An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth., , , and . HPCA, page 1-12. IEEE Computer Society, (2010)Design for pre-bond testability in 3D integrated circuits.. Georgia Institute of Technology, Atlanta, GA, USA, (2012)base-search.net (ftgeorgiatech:oai:smartech.gatech.edu:1853/45756).High Performance Non-blocking Switch Design in 3D Die-Stacking Technology., , and . ISVLSI, page 25-30. IEEE Computer Society, (2009)A scanisland based design enabling prebond testability in die-stacked microprocessors., and . ITC, page 1-8. IEEE Computer Society, (2007)Architectural evaluation of 3D stacked RRAM caches., and . 3DIC, page 1-4. IEEE, (2009)Testing Circuit-Partitioned 3D IC Designs., and . ISVLSI, page 139-144. IEEE Computer Society, (2009)