Author of the publication

An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth.

, , , and . HPCA, page 1-12. IEEE Computer Society, (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Chameleon: Virtualizing idle acceleration cores of a heterogeneous multicore processor for caching and prefetching., , , and . ACM Trans. Archit. Code Optim., 7 (1): 3:1-3:35 (2010)Pragmatic Integration of an SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV., , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (1): 1-13 (2013)Reducing energy of virtual cache synonym lookup using bloom filters., , , , and . CASES, page 179-189. ACM, (2006)COMPASS: a programmable data prefetcher using idle GPU shaders., and . ASPLOS, page 297-310. ACM, (2010)POD: A 3D-Integrated Broad-Purpose Acceleration Layer., , , , and . IEEE Micro, 28 (4): 28-40 (2008)An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth., , , and . HPCA, page 1-12. IEEE Computer Society, (2010)SIMD divergence optimization through intra-warp compaction., , , , and . ISCA, page 368-379. ACM, (2013)Active Channel Reservation for Coexistence Mechanism (ACROS) for IEEE 802.15.4 and IEEE 802.11., , , , and . IEICE Trans. Commun., 93-B (8): 2082-2087 (2010)Designing heterogeneous many-core processors to provide high performance under limited chip power budget.. Georgia Institute of Technology, Atlanta, GA, USA, (2010)base-search.net (ftgeorgiatech:oai:smartech.gatech.edu:1853/37294).SAFER: Stuck-At-Fault Error Recovery for Memories., , , , and . MICRO, page 115-124. IEEE Computer Society, (2010)