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Test embedding with discrete logarithms.

, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (5): 554-566 (1995)

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A Test and Maintenance Controller for a Module Containing Testable Chips., and . ITC, page 502-513. IEEE Computer Society, (1988)BALLAST: a methodology for partial scan design., , and . FTCS, page 118-125. IEEE Computer Society, (1989)SIESTA: a multi-facet scan design system., , , and . EURO-DAC, page 246-251. IEEE Computer Society Press, (1992)An O(n) algorithm for width determination of power/ground routes for VLSI circuits., and . Integr., 4 (4): 345-355 (1986)Built-in test for folded programmable logic arrays., and . Microprocess. Microsystems, 11 (6): 319-329 (1987)Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (5): 754-764 (2012)Scan Path with Look Ahead Shifting (SPLASH)., and . ITC, page 696-704. IEEE Computer Society, (1986)Some theoretical aspects of algorithmic routing., and . DAC, page 23-31. ACM, (1977)A class of min-cut placement algorithms.. DAC, page 284-290. ACM, (1977)Bounds on pseudoexhaustive test lengths., , and . IEEE Trans. Very Large Scale Integr. Syst., 6 (3): 420-431 (1998)