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Configuring multiple scan chains for minimum test time., , and . ICCAD, page 4-8. IEEE Computer Society / ACM, (1992)Keynote address tribute to Professor Mel Breuer: Contributions to CAD and Test., , , and . VTS, page 1. IEEE Computer Society, (2017)Reconfigurable scan chains: a novel approach to reduce test application time., and . ICCAD, page 710-715. IEEE Computer Society / ACM, (1993)Asynchronous multiple scan chain., and . VTS, page 270-276. IEEE Computer Society, (1995)An Efficient Scheme to Diagnose Scan Chains., and . ITC, page 704-713. IEEE Computer Society, (1997)Optimal Sequencing of Scan Registers., , and . ITC, page 293-302. IEEE Computer Society, (1992)TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model., , , , and . ISCA, page 114-123. IEEE Computer Society, (2004)Testability, Debuggability, and Manufacturability Features of the UltraSPARCTM-I Microprocessor., , , , , , , and . ITC, page 157-166. IEEE Computer Society, (1995)IODINE: a tool to automatically infer dynamic invariants for hardware designs., , , and . DAC, page 775-778. ACM, (2005)SIESTA: a multi-facet scan design system., , , and . EURO-DAC, page 246-251. IEEE Computer Society Press, (1992)