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Disambiguation of "Takashima, Daisaburo"

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Open/folded bit-line arrangement for ultra-high-density DRAM's.

, , , , and . IEEE J. Solid State Circuits, 29 (4): 539-542 (April 1994)

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Akira Takashima

Makoto Takashima

 

Other publications of authors with the same name

An Embedded DRAM Technology for High-Performance NAND Flash Memories., , , , , and . IEEE J. Solid State Circuits, 47 (2): 536-546 (2012)A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 46 (9): 2171-2179 (2011)Future system and memory architectures: Transformations by technology and applications., , and . ISSCC, page 530. IEEE, (2011)A cell transistor scalable DRAM array architecture., and . IEEE J. Solid State Circuits, 37 (5): 587-591 (2002)Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs., , , , , and . IEEE J. Solid State Circuits, 50 (5): 1324-1331 (2015)A 7T-SRAM With Data-Write Technique by Capacitive Coupling., , , , and . IEEE J. Solid State Circuits, 54 (2): 596-605 (2019)A 100 MHz Ladder FeRAM Design With Capacitance-Coupled-Bitline (CCB) Cell., , and . IEEE J. Solid State Circuits, 46 (3): 681-689 (2011)A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive., , , , , and . IEEE J. Solid State Circuits, 34 (11): 1557-1563 (1999)A novel power-off mode for a battery-backup DRAM., and . IEEE J. Solid State Circuits, 32 (1): 86-91 (1997)A 76-mm2 8-Mb chain ferroelectric memory., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 36 (11): 1713-1720 (2001)