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Disambiguation of "Watanabe, Shigeyoshi"

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Open/folded bit-line arrangement for ultra-high-density DRAM's.

, , , , and . IEEE J. Solid State Circuits, 29 (4): 539-542 (April 1994)

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Shigeyoshi Kawakatsu

Wataru Watanabe

Rie Watanabe

Norihiro Watanabe

Shigeo Watanabe

 

Other publications of authors with the same name

Circuit Design of Reconfigurable Logic Based on Double-Gate CNTFETs., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (7): 1642-1644 (2013)Design of a 128-mb SOI DRAM using the floating body cell (FBC)., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 41 (1): 135-145 (2006)An Adaptive Routing Algorithm of 2-D Torus Network Based on Turn Model: The Communication Performance., , , , and . Int. J. Netw. Comput., 5 (1): 223-238 (2015)MASSE: environment supporting for simulation and analysis of multiagent systems., , , , , , and . CTS, page 203-209. IEEE Computer Society, (2005)Adaptive routing algorithms and implementation for interconnection network TESH for parallel processing., , and . LCN, page 308-311. IEEE Computer Society, (2010)A Case Study of Applying SNA to Analyze CSCL Social Network., and . ICALT, page 18-20. IEEE Computer Society, (2007)Reconfigurable Dynamic Logic Circuit Generating t-Term Boolean Functions Based on Double-Gate CNTFETs., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 97-A (5): 1051-1058 (2014)Offset compensating bit-line sensing scheme for high density DRAM's., , and . IEEE J. Solid State Circuits, 29 (1): 9-13 (January 1994)The Performance Evaluation of a 3D Torus Network Using Partial Link-Sharing Method in NoC Router Buffer., , , and . IEICE Trans. Inf. Syst., 100-D (10): 2478-2492 (2017)An Adaptive Routing of the 2-D Torus Network Based on Turn Model., , , and . CANDAR, page 587-591. IEEE Computer Society, (2013)