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Modeling of Inherent Losses of Fully Integrated Switched Capacitor DC-DC Converters.

, , , and . J. Low Power Electron., 8 (5): 667-673 (2012)

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On the Analysis of Routing Cells and Adjacency Faults in CMOS Digital Circuits., , , and . DFT, page 263-270. IEEE Computer Society, (1994)BIST Architectures and Fault Emulation., , and . LATW, page 55-60. IEEE, (2006)Low power BIST by filtering non-detecting vectors., , , , , , , , , and . ETW, page 165-170. IEEE Computer Society, (1999)Low Power BIST by Filtering Non-Detecting Vectors., , , , , , , , , and . J. Electron. Test., 16 (3): 193-202 (2000)Ultra low power capless LDO with dynamic biasing of derivative feedback., , , and . Microelectron. J., 44 (2): 94-102 (2013)Modeling of Inherent Losses of Fully Integrated Switched Capacitor DC-DC Converters., , , and . J. Low Power Electron., 8 (5): 667-673 (2012)Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization., , , , and . PATMOS, volume 5349 of Lecture Notes in Computer Science, page 258-267. Springer, (2008)Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits., , , , , and . DDECS, page 34-37. IEEE Computer Society, (2008)A Probabilistic Method for the Computation of Testability of RTL Constructs., , , and . DATE, page 176-181. IEEE Computer Society, (2004)Predictive error detection by on-line aging monitoring., , , , , , , and . IOLTS, page 9-14. IEEE Computer Society, (2010)