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Transistor level automatic layout generator for non-complementary CMOS cells., and . VLSI-SoC, page 116-121. IEEE, (2007)A design flow for physical synthesis of digital cells with ASTRAN., , , , and . ACM Great Lakes Symposium on VLSI, page 245-246. ACM, (2014)Automated Synthesis of Cell Libraries for Asynchronous Circuits., , , , and . SBCCI, page 16:1-16:7. ACM, (2014)A study on layout quality of automatic generated cells., , , , and . ICECS, page 651-654. IEEE, (2010)An Educational Tool for Design Automation of CMOS Cells., , and . MSE, page 149-150. IEEE Computer Society, (2007)An automated design methodology for layout generation targeting power leakage minimization., , and . ICECS, page 81-84. IEEE, (2009)Low-sensitivity to process variations aging sensor for automotive safety-critical applications., , , , , , and . VTS, page 238-243. IEEE Computer Society, (2010)Predictive error detection by on-line aging monitoring., , , , , , , and . IOLTS, page 9-14. IEEE Computer Society, (2010)Automatic layout synthesis with ASTRAN applied to asynchronous cells., , , , and . LASCAS, page 1-4. IEEE, (2014)Efficient timing closure with a transistor level design flow., , , , and . VLSI-SoC, page 312-315. IEEE, (2007)