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VLSI architectures for polygon recognition., , and . IEEE Trans. Very Large Scale Integr. Syst., 1 (4): 398-407 (1993)SMAC: A VLSI Architecture for Scene Matching., , and . Real Time Imaging, 4 (3): 171-180 (1998)VLSI Architectures for Pattern Matching., and . IJPRAI, 8 (4): 815-843 (1994)VLSI Architectures for High-Speed Range Estimation., , and . IEEE Trans. Pattern Anal. Mach. Intell., 17 (9): 894-899 (1995)CASM: A VLSI Chip for Approximate String Matching., , and . IEEE Trans. Pattern Anal. Mach. Intell., 17 (8): 824-830 (1995)A VLSI Architecture for Approximate Tree Matching., and . IEEE Trans. Computers, 47 (3): 346-352 (1998)VLSI Architectures for Depth Estimation Using Intensity Gradient Analysis., , and . IPPS, page 700-704. IEEE Computer Society, (1993)A 9.6 GigaByte/s Throughput Plesiochronous Routing Chip., , , , and . COMPCON, page 261-266. IEEE Computer Society, (1996)SMAC: A Scene Matching Chip., , , , and . ICCD, page 184-187. IEEE Computer Society, (1993)PMAC: A Polygon Matching Chip., and . IJPRAI, 9 (2): 367-385 (1995)