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CNTFET Modeling and Reconfigurable Logic-Circuit Design.

I. O'Connor, J. Liu, F. Gaffiot, F. Prégaldiny, C. Lallement, C. Maneux, J. Goguet, S. Fregonese, T. Zimmer, L. Anghel, T. Dang, and R. Leveugle. IEEE Trans. Circuits Syst. I Regul. Pap., 54-I (11): 2365-2379 (2007)

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Pulsed I(V) - pulsed RF measurement system for microwave device characterization with 80ns/45GHz.M. Weis, S. Fregonese, M. Santorelli, A. Sahoo, C. Maneux, and T. Zimmer. ESSDERC, page 189-192. IEEE, (2012)Measurement based accurate definition of the SOA edges for SiGe HBTs.M. Jaoul, D. Céli, C. Maneux, and T. Zimmer. BCICTS, page 1-4. IEEE, (2019)Physics-based electrical compact model for monolayer Graphene FETs.J. Morales, S. Fregonese, C. Mukherjee, C. Maneux, T. Zimmer, W. Wei, and H. Happy. ESSDERC, page 240-243. IEEE, (2016)Qualitative assessment of epitaxial graphene FETs on SiC substrates via pulsed measurements and temperature variation.C. Mukherjee, S. Fregonese, T. Zimmer, C. Maneux, H. Happy, and D. Mele. ESSDERC, page 305-308. IEEE, (2014)Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design.Y. Wang, C. Mukherjee, H. Rezgui, M. Deng, C. Maneux, S. Mannaa, I. O'Connor, J. Müller, S. Pelloquin, and G. Larrieu. ESSDERC, page 57-60. IEEE, (2023)High current effects in InP/GaAsSb/InP DHBT: Physical mechanisms and parasitic effects.M. Belhaj, C. Maneux, N. Labat, A. Touboul, and P. Bove. Microelectron. Reliab., 43 (9-11): 1731-1736 (2003)Si/SiGe: C and InP/GaAsSb Heterojunction Bipolar Transistors for THz Applications.P. Chevalier, M. Schröter, C. Bolognesi, V. d'Alessandro, M. Alexandrova, J. Böck, R. Flickiger, S. Fregonese, B. Heinemann, C. Jungemann and 8 other author(s). Proc. IEEE, 105 (6): 1035-1050 (2017)Electro-Thermal Limitations and Device Degradation of SiGe HBTs with Emphasis on Circuit Performance.S. Fregonese, C. Mukherjee, H. Rücker, P. Chevalier, G. Fischer, D. Céli, M. Deng, M. Couret, F. Marc, C. Maneux and 1 other author(s). BCICTS, page 1-7. IEEE, (2021)InP DHBT Characterization up to 500 GHz and Compact Model Validation Towards THz Circuit Design.M. Deng, C. Mukherjee, N. Davy, V. Nodjiadjim, M. Riet, C. Mismer, J. Renaudier, M. Matos, and C. Maneux. BCICTS, page 1-4. IEEE, (2021)Substrate-coupling effect in BiCMOS technology for millimeter wave applications.S. Fregonese, R. D'Esposito, M. Matos, A. Kohler, C. Maneux, and T. Zimmer. NEWCAS, page 1-4. IEEE, (2015)

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CNTFET Modeling and Reconfigurable Logic-Circuit Design.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML CNTFET Modeling and Reconfigurable Logic-Circuit Design.

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CNTFET Modeling and Reconfigurable Logic-Circuit Design.