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Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design.

Y. Wang, C. Mukherjee, H. Rezgui, M. Deng, C. Maneux, S. Mannaa, I. O'Connor, J. Müller, S. Pelloquin, and G. Larrieu. ESSDERC, page 57-60. IEEE, (2023)

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Vera Mukherjee

Santanu Mukherjee

Oindrilla Mukherjee

Rick Mukherjee

Bhaskar Mukherjee

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Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design.Y. Wang, C. Mukherjee, H. Rezgui, M. Deng, C. Maneux, S. Mannaa, I. O'Connor, J. Müller, S. Pelloquin, and G. Larrieu. ESSDERC, page 57-60. IEEE, (2023)Electro-Thermal Limitations and Device Degradation of SiGe HBTs with Emphasis on Circuit Performance.S. Fregonese, C. Mukherjee, H. Rücker, P. Chevalier, G. Fischer, D. Céli, M. Deng, M. Couret, F. Marc, C. Maneux and 1 other author(s). BCICTS, page 1-7. IEEE, (2021)InP DHBT Characterization up to 500 GHz and Compact Model Validation Towards THz Circuit Design.M. Deng, C. Mukherjee, N. Davy, V. Nodjiadjim, M. Riet, C. Mismer, J. Renaudier, M. Matos, and C. Maneux. BCICTS, page 1-4. IEEE, (2021)1/f Noise in 3D vertical gate-all-around junction-less silicon nanowire transistors.C. Mukherjee, C. Maneux, J. Pezard, and G. Larrieu. ESSDERC, page 34-37. IEEE, (2017)InP DHBT test structure optimization towards 110 GHz characterization.N. Davy, M. Deng, V. Nodjiadjim, C. Mukherjee, M. Riet, C. Mismer, J. Renaudier, and C. Maneux. ESSDERC, page 320-323. IEEE, (2022)First Uni-Traveling Carrier Photodiode Compact Model Enabling Future Terahertz Communication System Design.C. Mukherjee, P. Mounaix, C. Maneux, M. Natrella, J. Seddon, C. Graham, and C. Renaud. ESSDERC, page 150-153. IEEE, (2019)InP DHBT Analytical Modeling: Toward THz Transistors.N. Davy, V. Nodjiadjim, M. Riet, C. Mismer, M. Deng, C. Mukherjee, B. Ardouin, and C. Maneux. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (11): 4102-4111 (November 2023)Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors.L. Réveil, C. Mukherjee, C. Maneux, M. Deng, F. Marc, A. Kumar, A. Lecestre, G. Larrieu, A. Poittevin, I. O'Connor and 2 other author(s). VLSI-SoC, page 1-2. IEEE, (2022)3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model.A. Poittevin, C. Mukherjee, I. O'Connor, C. Maneux, G. Larrieu, M. Deng, S. Beux, F. Marc, A. Lecestre, C. Marchand and 1 other author(s). VLSI-SoC (Selected Papers), volume 621 of IFIP Advances in Information and Communication Technology, page 301-321. Springer, (2020)A Logic Cell Design and routing Methodology Specific to VNWFET.A. Poittevin, I. O'Connor, C. Marchand, A. Bosio, C. Maneux, C. Mukherjee, G. Larrieu, and A. Kumar. NEWCAS, page 460-464. IEEE, (2022)

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Disambiguation of "Mukherjee, Chhandak"

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Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design.

Please choose a person to relate this publication to

Vera Mukherjee

Santanu Mukherjee

Oindrilla Mukherjee

Rick Mukherjee

Bhaskar Mukherjee

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Mukherjee, Chhandak"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design.

Please choose a person to relate this publication to

Vera Mukherjee

Santanu Mukherjee

Oindrilla Mukherjee

Rick Mukherjee

Bhaskar Mukherjee

Other publications of authors with the same name

Disambiguation

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Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design.