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An IDDQ sensor for concurrent timing error detection., , и . IEEE J. Solid State Circuits, 33 (10): 1545-1550 (1998)A Modular Fault-Tolerant Binary Tree Architecture with Short Links., и . IEEE Trans. Computers, 40 (7): 882-890 (1991)Test application time minimization for RAS using basis optimization of column decoder., , , , и . ISCAS, стр. 2614-2617. IEEE, (2010)Special session: Hot topics: Statistical test methods., , , , , и . VTS, стр. 1-2. IEEE Computer Society, (2015)Exploiting path delay test generation to develop better TDF tests for small delay defects., , , и . ITC, стр. 1-10. IEEE, (2017)Estimating Operational Age of an Integrated Circuit., , , и . J. Electron. Test., 37 (1): 25-40 (2021)Aging-Resilient SRAM-based True Random Number Generator for Lightweight Devices., , и . J. Electron. Test., 36 (3): 301-311 (2020)Scan based two-pattern tests: should they target opens instead of TDFs?. LATS, стр. 1-2. IEEE Computer Society, (2015)Silent Data Errors: Sources, Detection, and Modeling., , , и . VTS, стр. 1-12. IEEE, (2023)Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing., и . VLSI Design, стр. 763-768. IEEE Computer Society, (2007)