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Disambiguation of "Sato, Toshinori"

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Importance of Single-Core Performance in the Multicore Era.

, , , and . ACSC, volume 122 of CRPIT, page 107-114. Australian Computer Society, (2012)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Toshinori Kuwahara

Makoto Sato

Nobuko Sato

Fujio Sato

Satô Saburô

 

Other publications of authors with the same name

The KIT COSMOS Processor: An Application of Multi-Threading for Dynamic Optimization., , , and . PDPTA, page 1010-1016. CSREA Press, (2002)Improving timing error tolerance without impact on chip area and power consumption., , and . ISQED, page 373-378. IEEE, (2013)Exploiting Configurability for Correct Sign Calculation in an Approximate Adder., and . ISOCC, page 86-87. IEEE, (2018)The potential in energy efficiency of a speculative chip-multiprocessor., , and . SPAA, page 273-274. ACM, (2004)Realizing Energy-Efficient MultiCore Processors by Utilizing Speculative Thread-Level Parallelism., , , , , and . Int. J. Comput. Their Appl., 14 (2): 79-91 (2007)A Selective Replacement Method for Timing-Error-Predicting flip-Flops., , , and . J. Circuits Syst. Comput., (2012)Topic 4: High-Performance Architecture and Compilers., , , and . Euro-Par, volume 7484 of Lecture Notes in Computer Science, page 204-205. Springer, (2012)2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3D graphics computing., , , , , , , , , and . IEEE J. Solid State Circuits, 35 (7): 1025-1033 (2000)Exploiting Configurable Approximations for Tolerating Aging-induced Timing Violations., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 103-A (9): 1028-1036 (2020)Non-uniform Set-Associative Caches for Power-Aware Embedded Processors., and . EUC, volume 3207 of Lecture Notes in Computer Science, page 217-226. Springer, (2004)