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A Hierarchical Multiprocessor Achitecture for Video Coding Applications.

, , and . ISCAS, page 1750-1753. IEEE, (1993)

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Coding Algorithms and VLSI Implementations for Digital TV and HDTV Satellite Broadcasting., and . Eur. Trans. Telecommun., 4 (1): 11-21 (1993)Circuit Technique for VLSI Design of a Video Codec., , and . ICC (1), page 250-255. Elsevier, (1984)VLSI implementations of image and video multimedia processing systems., and . IEEE Trans. Circuits Syst. Video Techn., 8 (7): 878-891 (1998)Von abstrakten Architekturtemplates zur hardwarenahen Architekturexploration., and . GI Jahrestagung (1), volume P-67 of LNI, page 458. GI, (2005)Instruction merging to increase parallelism in VLIW architectures., , , , and . SoC, page 143-146. IEEE, (2009)A 1.3-GOPS parallel DSP for high-performance image-processing applications., , , , , and . IEEE J. Solid State Circuits, 35 (7): 946-952 (2000)Experimental violation of the Start-Stop-Approximation using a Holistic Rail-based UWB FMCW-SAR System, , , and . EUSAR 2016: 11th European Conference on Synthetic Aperture Radar, Proceedings of, page 1--4. VDE VERLAG GmbH, (2016)Multiprocessor performance for real-time processing of video coding applications., , and . IEEE Trans. Circuits Syst. Video Techn., 2 (2): 221-230 (1992)VLSI components for a 560-Mbit/s HDTV codec., , , and . VCIP, volume 1360 of SPIE Proceedings, SPIE, (1990)Design of a development system for multimedia applications based on a single chip multiprocessor array., , , and . ICECS, page 1151-1154. IEEE, (1996)