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Disambiguation of "Wadatsumi, Junji"

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19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension.

, , , , , , , , , , , , , and . ISSCC, page 330-331. IEEE, (2014)

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Junji Liu

Junji Kato

 

Other publications of authors with the same name

Polar Antenna Impedance Detection and Tuning for Efficiency Improvement in a 3G/4G CMOS Power Amplifier., , , , , and . IEEE J. Solid State Circuits, 49 (12): 2902-2914 (2014)A Fully Integrated 2 ˟ 1 Dual-Band Direct-Conversion Mobile WiMAX Transceiver With Dual-Mode Fractional Divider and Noise-Shaping Transimpedance Amplifier in 65 nm CMOS., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 45 (12): 2774-2784 (2010)19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension., , , , , , , , , and 4 other author(s). ISSCC, page 330-331. IEEE, (2014)A 12.8 GB/S Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth and Large-Capacity Storage Systems., , , , , , , and . VLSI Circuits, page 149-150. IEEE, (2018)A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems., , , , , , , , and . IEEE J. Solid State Circuits, 54 (4): 1086-1095 (2019)A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 57 (5): 1517-1526 (2022)A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Scheme for Mueller-Müller CDR., , , , , , , , , and . ESSCIRC, page 505-508. IEEE, (2022)A 1.2V 0.2-to-6.3GHz Transceiver with Less Than -29.5dB EVM@-3dBm and a Choke/Coil-Less Pre-Power Amplifier., , , , , , and . ISSCC, page 214-215. IEEE, (2008)A 25.6Gb/s Uplink-Downlink Interface Employing PAM-4-Based 4-Channel Multiplexing and Cascaded CDR Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems., , , , , , , , , and 2 other author(s). ISSCC, page 478-480. IEEE, (2019)A fully integrated 2×1 dual-band direct-conversion transceiver with dual-mode fractional divider and noise-shaping TIA for mobile WiMAX SoC in 65nm CMOS., , , , , , , , , and 3 other author(s). ISSCC, page 456-457. IEEE, (2010)