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Efficient Memory-Addressing Algorithms for FFT Processor Design., , и . IEEE Trans. Very Large Scale Integr. Syst., 23 (10): 2162-2172 (2015)A New Modular Exponentiation Architecture for Efficient Design of RSA Cryptosystem., , , и . IEEE Trans. Very Large Scale Integr. Syst., 16 (9): 1151-1161 (2008)Reducing Interconnect Complexity for Efficient Path Metric Memory Management in Viterbi Decoders., , и . IEICE Trans. Inf. Syst., 91-D (9): 2300-2311 (2008)High-Speed Design of Montgomery Inverse Algorithm over GF(2m)., , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (2): 559-565 (2006)A New Algorithm for High-Speed Modular Multiplication Design., , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (9): 2009-2019 (2009)A low-latency turbo decoding scheme for diversities-based communication systems., , , и . ICSPCS, стр. 1-6. IEEE, (2012)A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem., , , , и . ISCAS (1), стр. 500-503. IEEE, (1999)A novel adaptive algorithm and VLSI design for frequency detection in noisy environment based on adaptive IIR filter., , , и . ISCAS (4), стр. 446-449. IEEE, (2001)VLSI architecture of extended in-place path metric update for Viterbi decoders., , , и . ISCAS (4), стр. 206-209. IEEE, (2001)An efficient countermeasure against power attacks for ECC over GF(p)., , и . ISCAS, стр. 814-817. IEEE, (2014)