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D-RaNGe: Violating DRAM Timing Constraints for High-Throughput True Random Number Generation using Commodity DRAM Devices.

, , , , and . CoRR, (2018)

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AVPP: Address-first Value-next Predictor with Value Prefetching for Improving the Efficiency of Load Value Prediction., , and . ACM Trans. Archit. Code Optim., 15 (4): 49:1-49:30 (2019)ALP: Alleviating CPU-Memory Data Movement Overheads in Memory-Centric Systems., , , , , , , , , and . IEEE Trans. Emerg. Top. Comput., 11 (2): 388-403 (April 2023)DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators., , , , , , , and . HPCA, page 1141-1155. IEEE, (2022)pLUTo: Enabling Massively Parallel Computation In DRAM via Lookup Tables., , , , , , , , , and 1 other author(s). (July 2022)A Hardware Approach to Detect, Expose and Tolerate High Level Data Races., and . PDP, page 159-167. IEEE Computer Society, (2016)ITAP: Idle-Time-Aware Power Management for GPU Execution Units., , , , , , , , , and . ACM Trans. Archit. Code Optim., 16 (1): 3:1-3:26 (2019)ALP: Alleviating CPU-Memory Data Movement Overheads in Memory-Centric Systems., , , , , , , , , and . CoRR, (2022)NEON: Enabling Efficient Support for Nonlinear Operations in Resistive RAM-based Neural Network Accelerators., , , , , , and . CoRR, (2022)DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks., , , , , , , and . CoRR, (2021)D-RaNGe: Violating DRAM Timing Constraints for High-Throughput True Random Number Generation using Commodity DRAM Devices., , , , and . CoRR, (2018)