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SMASH: Co-designing Software Compression and Hardware-Accelerated Indexing for Efficient Sparse Matrix Operations., , , , , , , , and . CoRR, (2019)D-RaNGe: Violating DRAM Timing Constraints for High-Throughput True Random Number Generation using Commodity DRAM Devices., , , , and . CoRR, (2018)Efficient Document Analytics on Compressed Data: Method, Challenges, Algorithms, Insights., , , , and . Proc. VLDB Endow., 11 (11): 1522-1535 (2018)NoM: Network-on-Memory for Inter-Bank Data Transfer in Highly-Banked Memories., , , , , and . IEEE Comput. Archit. Lett., 19 (1): 80-83 (2020)Exploiting the DRAM Microarchitecture to Increase Memory-Level Parallelism., , , , and . CoRR, (2018)A Workload and Programming Ease Driven Perspective of Processing-in-Memory., , , , and . CoRR, (2019)Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators., , , and . CoRR, (2019)Automatic Generation of Warp-Level Primitives and Atomic Instructions for Fast and Portable Parallel Reduction on GPUs., , , , , and . CGO, page 73-84. IEEE, (2019)Extending Memory Capacity in Modern Consumer Systems With Emerging Non-Volatile Memory: Experimental Analysis and Characterization Using the Intel Optane SSD., , , , , , , , , and 1 other author(s). IEEE Access, (2023)RFVP: Rollback-Free Value Prediction with Safe-to-Approximate Loads., , , , , and . ACM Trans. Archit. Code Optim., 12 (4): 62:1-62:26 (2016)