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ScaLP: A Light-Weighted (MI)LP-Library.

, , , и . MBMV, Universität Tübingen, (2018)

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Elisabeth Kumm

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Renate Kumm

 

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Digital hilbert transformers for FPGA-based phase-locked loops., и . FPL, стр. 251-256. IEEE, (2008)Design of Optimal Multiplierless FIR Filters With Minimal Number of Adders., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (2): 658-671 (февраля 2023)Optimal Single Constant Multiplication Using Ternary Adders., , , и . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (7): 928-932 (2018)More AddNet: A deeper insight into DNNs using FPGA-optimized multipliers., , , , , и . ISCAS, стр. 1-5. IEEE, (2023)Hardware-Aware Quantization for Multiplierless Neural Network Controllers., , , и . APCCAS, стр. 541-545. IEEE, (2022)Resource Optimal Truncated Multipliers for FPGAs., , и . ARITH, стр. 102-109. IEEE, (2021)Karatsuba with Rectangular Multipliers for FPGAs., , , , и . ARITH, стр. 13-20. IEEE, (2018)Table-Based versus Shift-And-Add Constant Multipliers for FPGAs., , , и . ARITH, стр. 151-158. IEEE, (2019)Heuristics for the Design of Large Multipliers for FPGAs., , и . ARITH, стр. 17-24. IEEE, (2020)Comparison of Arithmetic Number Formats for Inference in Sum-Product Networks on FPGAs., , , и . FCCM, стр. 75-83. IEEE, (2020)