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A Partial Scan Based Test Generation for Asynchronous Circuits., and . DDECS, page 186-189. IEEE Computer Society, (2008)Adaptive Pipeline Depth Control for Processor Power-Management., and . ICCD, page 454-457. IEEE Computer Society, (2002)Fast, Parallel Two-Rail Code Checker with Enhanced Testability., , , , and . IOLTS, page 149-156. IEEE Computer Society, (2005)Signal decoding in an NLOS VLC system with the presence of anti-reflective obstacles., , , , , , and . BlackSeaCom, page 303-309. IEEE, (2022)Deep Learning Based Detection of Anti-Reflective Obstacles in VLC Systems., , , , , , and . ICAIIC, page 401-406. IEEE, (2024)Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive Combinational Circuits.. DDECS, page 377-382. IEEE Computer Society, (2007)Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits., , and . DATE, page 672-673. IEEE Computer Society, (2004)Adaptive Pipeline Structures fo Speculation Control., and . ASYNC, page 46-55. IEEE Computer Society, (2003)An efficient adaptive thresholding scheme for signal decoding in NLOS VLC systems., , , , , , and . MeditCom, page 378-382. IEEE, (2021)Adding Testability to an Asynchronous Interconnect for GALS SoC., , and . Asian Test Symposium, page 20-23. IEEE Computer Society, (2004)