Author of the publication

An I/Q-multiplexed and OTA-shared CMOS pipelined ADC with an A-DQS S/H front-end for two-step-channel-select low-IF receiver.

, , , , , , , and . ISCAS (1), page 1068-1071. IEEE, (2004)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits., , and . ISCAS, IEEE, (2006)A frequency up-conversion and two-step channel selection embedded CMOS D/A interface., , , , and . ISCAS (1), page 392-395. IEEE, (2005)A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations., , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (1): 354-363 (2017)A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Δ Σ Modulator With Multirate Opamp Sharing., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (10): 2641-2654 (2017)An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H., , , , , , , , and . ESSCIRC, page 218-221. IEEE, (2010)New impulse sampled IIR switched-capacitor interpolators., , and . ICECS, page 203-206. IEEE, (1996)A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC., , , , and . VLSIC, page 90-91. IEEE, (2012)Jitter-resistant Capacitor Based Sine-Shaped DAC for Continuous-Time Sigma-Delta modulators., , , , and . ISCAS, page 1348-1351. IEEE, (2014)A 1.2V 86dB SNDR 500kHz BW Linear-Exponential Multi-Bit Incremental ADC Using Positive Feedback in 65nm CMOS., , , , and . A-SSCC, page 117-120. IEEE, (2019)A 5-bit 2 GS/s binary-search ADC with charge-steering comparators., , , , and . A-SSCC, page 221-224. IEEE, (2017)