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A 16-bit 65-MS/s Pipeline ADC With 80-dBFS SNR Using Analog Auto-Calibration in SiGe SOI Complementary BiCMOS., and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (8): 2166-2177 (2008)11.6 A 21mW 15b 48MS/s zero-crossing pipeline ADC in 0.13μm CMOS with 74dB SNDR., , , , , , , , and . ISSCC, page 204-205. IEEE, (2014)A 1.4-V 10-bit 25-MS/s pipelined ADC using opamp-reset switching technique., and . IEEE J. Solid State Circuits, 38 (8): 1401-1404 (2003)Design techniques for a pipelined ADC without using a front-end sample-and-hold amplifier.. IEEE Trans. Circuits Syst. I Regul. Pap., 51-I (11): 2123-2132 (2004)Radix-based digital calibration techniques for multi-stage recycling pipelined ADCs., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 51-I (11): 2133-2140 (2004)A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators., , , , , , , , , and . IEEE J. Solid State Circuits, 40 (12): 2398-2407 (2005)Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 52-I (1): 1-12 (2005)A low-Voltage 10-bit CMOS DAC in 0.01-mm2 die area., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 52-II (5): 246-250 (2005)A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR., , , and . IEEE J. Solid State Circuits, 40 (4): 960-969 (2005)Design techniques for a low-power low-cost CMOS A/D converter., and . IEEE J. Solid State Circuits, 33 (8): 1244-1248 (1998)