Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Hierarchical Scheduling in High Level Synthesis Using Resource Sharing Across Nested Loops., , and . Great Lakes Symposium on VLSI, page 140-143. IEEE Computer Society, (1999)Regularized Stacked Auto-Encoder Based Pre-training for Generalization of Multi-layer Perceptron., , and . TPNC, volume 10687 of Lecture Notes in Computer Science, page 232-242. Springer, (2017)YAML: A Tool for Hardware Design Visualization and Capture., , , , , and . ISSS, page 9-17. ACM / IEEE Computer Society, (2000)Sequential logic synthesis for testability using register-transfer level descriptions., , and . ITC, page 274-283. IEEE Computer Society, (1990)Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test., , , and . ICCAD, page 84-87. IEEE Computer Society, (1990)Sequential Test Generation at the Register-Transfer and Logic Levels., , and . DAC, page 580-586. IEEE Computer Society Press, (1990)Verification of Interacting Sequential Circuits., , and . DAC, page 213-219. IEEE Computer Society Press, (1990)Recent progress in synthesis for testability., , and . VTS, page 22-29. IEEE Computer Society, (1991)An observability-based code coverage metric for functional simulation., , and . ICCAD, page 418-425. IEEE Computer Society / ACM, (1996)Precomputation-based sequential logic optimization for low power., , , , and . ICCAD, page 74-81. IEEE Computer Society / ACM, (1994)