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32nm and beyond Multi-VT Ultra-Thin Body and BOX FDSOI: From device to circuit., , , , , , , , , and 4 other author(s). ISCAS, page 1703-1706. IEEE, (2010)Multibranch mobility characterization: Evidence of carrier mobility enhancement by back-gate biasing in FD-SOI MOSFET., , , , , , , , and . ESSDERC, page 209-212. IEEE, (2012)Precise EOT regrowth extraction enabling performance analysis of low temperature extension first devices., , , , , , , , , and 5 other author(s). ESSDERC, page 144-147. IEEE, (2017)Intermediate BEOL process influence on power and performance for 3DVLSI., , , , , , , and . 3DIC, page TS1.3.1-TS1.3.5. IEEE, (2015)FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration., , , , , , , , , and 6 other author(s). ESSDERC, page 110-113. IEEE, (2014)Benefit of Al2O3/HfO2 bilayer for BEOL RRAM integration through 16kb memory cut characterization., , , , , , , , , and 6 other author(s). ESSDERC, page 266-269. IEEE, (2015)Transistor Temperature Deviation Analysis in Monolithic 3D Standard Cells., , , , , , , , , and 2 other author(s). ISVLSI, page 539-544. IEEE Computer Society, (2017)Recent advances in 3D VLSI integration., , , , , , , , , and 7 other author(s). ICICDT, page 1-4. IEEE, (2016)Opportunities brought by sequential 3D CoolCube™ integration., , , , , , , , , and 11 other author(s). ESSDERC, page 226-229. IEEE, (2016)Guidelines for intermediate back end of line (BEOL) for 3D sequential integration., , , , , , , , , and 18 other author(s). ESSDERC, page 252-255. IEEE, (2017)