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Evaluating the accuracy of SRAM margin simulation through large scale Monte-Carlo simulations with accurate compact models.

P. Asenov, D. New, D. Reid, C. Millar, S. Roy, and A. Asenov. ICICDT, page 29-32. IEEE, (2013)

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Plamen Pironkov

Numerical simulation of thermal fluid-structure interactionP. Pironkov. TU Darmstadt, (2010)

Plamen Turkedjiev

Plamen Simeonov

Plamen Kasabov

Plamen Nikolow

Other publications of authors with the same name

Modeling and Simulation for DRAM and Flash Memory Technology Exploration and Development.X. Lin, S. Amoroso, K. Lee, M. Ke, T. Gunst, P. Tikhomirov, and P. Asenov. IMW, page 1-4. IEEE, (2024)Evaluating the accuracy of SRAM margin simulation through large scale Monte-Carlo simulations with accurate compact models.P. Asenov, D. New, D. Reid, C. Millar, S. Roy, and A. Asenov. ICICDT, page 29-32. IEEE, (2013)TCAD based Design-Technology Co-Optimisations in advanced technology nodes.A. Asenov, K. Sayed, R. Borges, P. Asenov, C. Millar, and T. Ma. VLSI-DAT, page 1-2. IEEE, (2017)An advanced statistical compact model strategy for SRAM simulation at reduced VDD.P. Asenov, D. Reid, S. Roy, C. Millar, and A. Asenov. ESSDERC, page 205-208. IEEE, (2012)Modeling of Negative Bias Temperature Instability (NBTI) for Gate-All-Around (GAA) Stacked Nanosheet Technology.L. Liu, J. Fang, A. Pal, P. Asenov, M. Bajaj, B. Deng, X. Lin, S. Mahapatra, S. Kengeri, and E. Bazizi. IRPS, page 7. IEEE, (2024)Nanowire transistor solutions for 5nm and beyond.A. Asenov, Y. Wang, B. Cheng, X. Wang, P. Asenov, T. Al-Ameri, and V. Georgiev. ISQED, page 269-274. IEEE, (2016)Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis.M. Merrett, P. Asenov, Y. Wang, M. Zwolinski, D. Reid, C. Millar, S. Roy, Z. Liu, S. Furber, and A. Asenov. DATE, page 1537-1540. IEEE, (2011)Unified approach for simulation of statistical reliability in nanoscale CMOS transistors from devices to circuits.A. Asenov, J. Ding, D. Reid, P. Asenov, S. Amoroso, F. Adamu-Lema, and L. Gerrer. ISCAS, page 2449-2452. IEEE, (2015)Exploring Power Savings of Gate-All-Around Cryogenic Technology.V. Moroz, A. Svizhenko, M. Choi, P. Asenov, and J. Lee. VLSI Technology and Circuits, page 1-2. IEEE, (2023)

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Disambiguation of "Asenov, Plamen"

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Evaluating the accuracy of SRAM margin simulation through large scale Monte-Carlo simulations with accurate compact models.

Please choose a person to relate this publication to

Plamen Pironkov

Plamen Turkedjiev

Plamen Simeonov

Plamen Kasabov

Plamen Nikolow

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Asenov, Plamen"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Evaluating the accuracy of SRAM margin simulation through large scale Monte-Carlo simulations with accurate compact models.

Please choose a person to relate this publication to

Plamen Pironkov

Plamen Turkedjiev

Plamen Simeonov

Plamen Kasabov

Plamen Nikolow

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Evaluating the accuracy of SRAM margin simulation through large scale Monte-Carlo simulations with accurate compact models.