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Disambiguation of "Paolucci, Pier Stanislao"

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Real-time cortical simulations: energy and interconnect scaling on distributed systems.

, , , , , , , , , , , , , and . CoRR, (2018)

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Stanislao Morgera

Waltraud Pier

Waltraud Pier

Arnold Pier

Bernhard Pier

 

Other publications of authors with the same name

The APE-100 Computer: (I) the Architecture., , , , , , , , , and 10 other author(s). Int. J. High Speed Comput., 5 (4): 637-656 (1993)Fast Simulation of a Multi-Area Spiking Network Model of Macaque Cortex on an MPI-GPU Cluster., , , , , , , , , and . Frontiers Neuroinformatics, (August 2022)Distributed simulation of polychronous and plastic spiking neural networks: strong and weak scaling of a representative mini-application benchmark executed on a small-scale commodity cluster., , , , , , , , , and . CoRR, (2013)Design and implementation of a modular, low latency, fault-aware, FPGA-based network interface., , , , , , , , , and . ReConFig, page 1-6. IEEE, (2013)ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces., , , , , , , , , and 2 other author(s). Future Gener. Comput. Syst., (2015)Real-Time Cortical Simulations: Energy and Interconnect Scaling on Distributed Systems., , , , , , , , , and 4 other author(s). PDP, page 283-290. IEEE, (2019)NaNet: a Low-Latency, Real-Time, Multi-Standard Network Interface Card with GPUDirect Features., , , , , , , , , and 7 other author(s). CoRR, (2014)Scaling to 1024 software processes and hardware cores of the distributed simulation of a spiking neural network including up to 20G synapses., , , , , , , , , and . CoRR, (2015)Large Scale Low Power Computing System - Status of Network Design in ExaNeSt and EuroExa Projects., , , , , , , , , and 3 other author(s). CoRR, (2018)The colours of the Higgs boson: a study in creativity and science motivation among high-school students in Italy., , , , , , , , , and . Smart Learn. Environ., 8 (1): 23 (2021)