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Disambiguation of "Mitsuyama, Yukio"

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A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch.

, , , , , , , , , , and . FPL, page 1-4. IEEE, (2016)

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Yukio Matsudo

Yukio Yamanaka

Yukio Kamizuru

Yukio Ozawa

 

Other publications of authors with the same name

VLSI architecture of dynamically reconfigurable hardware-based cipher., , , and . ISCAS (4), page 734-737. IEEE, (2001)Burst mode: a new acceleration mode for 128-bit block ciphers., , , and . CICC, page 151-154. IEEE, (2002)A predictive delay fault avoidance scheme for coarse-grained reconfigurable architecture., , , , , and . FPL, page 615-618. IEEE, (2012)A dynamically reconfigurable hardware-based cipher chip., , , and . ASP-DAC, page 11-12. ACM, (2001)Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture., , , , , , , , , and 4 other author(s). IEEE Embed. Syst. Lett., 10 (4): 119-122 (2018)Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits., , , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (2): 333-343 (2012)33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications., , , , , , , , , and 4 other author(s). ISSCC, page 502-504. IEEE, (2020)Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits., , , and . ASP-DAC, page 361-362. IEEE, (2010)Static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devices., , , and . ReConFig, page 1-7. IEEE, (2012)Coarse-grained dynamically reconfigurable architecture with flexible reliability., , , , , , , , and . FPL, page 186-192. IEEE, (2009)