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Disambiguation of "Tsai, Chia-Chun"

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An Efficiently Hardware-Software Partitioning for Embedded Multiprocessor FPGA Systems.

, , , , and . IMECS, page 346-351. Newswood Limited, (2007)

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Chia-Chun Lu

Chia-Chun Liang

Chia-chun Gu

Yu-Chun Tsai

Yin-chun Tsai-Stürenberg

 

Other publications of authors with the same name

Using Stack Reconstruction on RTL Orthogonal Scan Chain Design., , , , and . J. Inf. Sci. Eng., 22 (6): 1585-1599 (2006)An H-V Tile-Expansion Router., , and . J. Inf. Sci. Eng., 6 (3): 173-189 (1990)Performance driven bus buffer insertion., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (4): 429-437 (1996)NEWS: a net-even-wiring system for the routing on a multilayer PGA package., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (2): 182-189 (1998)An H-V alternating router., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 11 (8): 976-991 (1992)Antenna Violation Avoidance/Fixing for X-clock routing., , , and . ISQED, page 508-514. IEEE, (2010)Coupling aware RLC-based clock routings for crosstalk minimization., , , , and . ISCAS, IEEE, (2006)X-clock routing based on pattern matching., , , , and . SoCC, page 357-360. IEEE, (2008)A Bisection-Based Power Reduction Design for CMOS Flash Analog-to-Digital converters., , and . Journal of Circuits, Systems, and Computers, 18 (5): 933-945 (2009)A Low Complexity PMI Selection Scheme for 3GPP 5G NR FDD Systems., , , , and . APSIPA ASC, page 1917-1922. IEEE, (2021)