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Disambiguation of "Aymerich, Nivard"

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New reliability mechanisms in memory design for sub-22nm technologies.

, , , , , , , , , , , , , , , , and . IOLTS, page 111-114. IEEE Computer Society, (2011)

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Ursmar Nivard Kleiner

 

Other publications of authors with the same name

Extending the fundamental error bounds for asymmetric error reliable computation., and . NANOARCH, page 106-109. IEEE Computer Society, (2013)Systematic and random variability analysis of two different 6T-SRAM layout topologies., , , , , , and . Microelectron. J., 44 (9): 787-793 (2013)Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells., , , , and . ACM Great Lakes Symposium on VLSI, page 277-282. ACM, (2011)Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells., , , , and . Integr., 45 (3): 246-252 (2012)Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm., , , , and . Microelectron. J., 45 (10): 1342-1347 (2014)New reliability mechanisms in memory design for sub-22nm technologies., , , , , , , , , and 7 other author(s). IOLTS, page 111-114. IEEE Computer Society, (2011)Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy., and . Microprocess. Microsystems, 36 (5): 420-426 (2012)Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip., , , , , , , , , and 23 other author(s). HCS, page 1-23. IEEE, (2021)Variability robustness enhancement for 7nm FinFET 3T1D-DRAM cells., , , , and . MWSCAS, page 81-84. IEEE, (2013)