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An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration.

, , , , and . DATE, page 878-883. IEEE Computer Society, (2004)

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An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration., , , , and . DATE, page 878-883. IEEE Computer Society, (2004)A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification., , , , , and . DATE, page 1182-1187. IEEE Computer Society, (2005)Translating Imperative Affine Nested Loop Programs into Process Networks., , and . Embedded Processor Design Challenges, volume 2268 of Lecture Notes in Computer Science, page 89-111. Springer, (2002)High Level Modeling for Parallel Executions of Nested Loop Algorithms., , , and . ASAP, page 79-91. IEEE Computer Society, (2000)Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach., , , , and . DATE, page 764-769. IEEE Computer Society, (2004)A strategy for determining a Jacobi specific dataflow processor., , , and . ASAP, page 53-. IEEE Computer Society, (1997)Deadlock Prevention in the Æthereal Protocol., , , , , and . CHARME, volume 3725 of Lecture Notes in Computer Science, page 345-348. Springer, (2005)An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (1): 4-17 (2005)Guaranteeing the Quality of Services in Networks on Chip., , , , , , , and . Networks on Chip, Kluwer / Springer, (2003)Deriving Process Networks from Nested Loop Algorithms., , and . Parallel Process. Lett., 10 (2/3): 165-176 (2000)