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Disambiguation of "Otsuga, Kazuo"

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Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node.

, , , , , , , , , and . IEEE J. Solid State Circuits, 42 (6): 1362-1369 (2007)

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Kazuo Inoue

Kazuo Okohira

Kazuo Yajima

Kazuo Araki

Kazuo OÌ no

 

Other publications of authors with the same name

A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process., , , , , , and . A-SSCC, page 37-40. IEEE, (2011)A Design of Constant-Charge-Injection Programming Scheme for AG-AND Flash Memories Using Array-Level Analytical Model., , , , and . IEICE Trans. Electron., 91-C (4): 526-533 (2008)An on-chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage sensor., , , , , , and . SoCC, page 11-14. IEEE, (2012)Constant-charge-injection programming: a novel high-speed programming method for multilevel flash memories., , , , , , and . IEEE J. Solid State Circuits, 40 (2): 523-531 (2005)Testability improvement for 12.8 GB/s Wide IO DRAM controller by small area pre-bonding TSV tests and a 1 GHz sampled fully digital noise monitor., , , , , , , , , and 3 other author(s). CICC, page 1-4. IEEE, (2013)Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node., , , , , , , , , and . IEEE J. Solid State Circuits, 42 (6): 1362-1369 (2007)A 126 mm2 4-Gb Multilevel AG-AND Flash Memory with Inversion-Layer-Bit-Line Technology., , , , , , , , , and 5 other author(s). IEICE Trans. Electron., 90-C (11): 2146-2156 (2007)Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AG-AND Flash Memories., , , , , , and . IEICE Trans. Electron., 90-C (4): 772-778 (2007)