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Disambiguation of "Kamohara, Shiro"

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Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node.

, , , , , , , , , and . IEEE J. Solid State Circuits, 42 (6): 1362-1369 (2007)

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Shiro Kobayashi

Shiro Takebayashi

Shiro Kobayashi

Shiro Yukawa

Shiro Ando

 

Other publications of authors with the same name

Analysis of SRAM neutron-induced errors based on the consideration of both charge-collection and parasitic-bipolar failure modes., , , and . CICC, page 357-360. IEEE, (2004)Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node., , , , , , , , , and . IEEE J. Solid State Circuits, 42 (6): 1362-1369 (2007)A Silicon-on-Thin-Buried-Oxide CMOS Microcontroller with Embedded Atom-Switch ROM., , , , , , , , , and 8 other author(s). IEEE Micro, 35 (6): 13-23 (2015)SOTB (Silicon on Thin Buried Oxide): More than Moore technology for IoT and Automotive., , , , , and . ICICDT, page 1-4. IEEE, (2017)Circuit performance oriented device optimization using BSIM3 pre-silicon model parameters., and . ASP-DAC, page 371-374. ACM, (2000)A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology., , , , , , , , , and 15 other author(s). COOL Chips, page 1-3. IEEE Computer Society, (2014)Repair Yield Simulation with Iterative Critical Area Analysis for Different Types of Failure., , , , , , and . DFT, page 305-313. IEEE Computer Society, (2002)A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode., , , , , , and . IEICE Trans. Electron., 98-C (7): 536-543 (2015)Pre-silicon parameter generation methodology using BSIM3 for device/circuit concurrent design., , , , and . CICC, page 359-363. IEEE, (1999)0.39-V, 18.26-µW/MHz SOTB CMOS Microcontroller with embedded atom switch ROM., , , , , , , , , and 8 other author(s). COOL Chips, page 1-3. IEEE Computer Society, (2015)