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Disambiguation of "Meher, Pramod Kumar"

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Hardware-Efficient Realization of Prime-Length DCT Based on Distributed Arithmetic.

, , and . IEEE Trans. Computers, 62 (6): 1170-1178 (2013)

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Pramod Kumar Pandey

Pramod Kumar Magu

Pramod Kumar Bhatotia

Pramod Chandrashekhariah

Pramod Shah

 

Other publications of authors with the same name

An optimized design for serial-parallel finite field multiplication over GF(2m) based on all-one polynomials., , and . ASP-DAC, page 210-215. IEEE, (2009)Efficient bit-parallel multipliers over finite fields GF(2m)., and . Comput. Electr. Eng., 36 (5): 955-968 (2010)Low Latency Systolic Montgomery Multiplier for Finite Field $GF(2^m)$ Based on Pentanomials., , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (2): 385-389 (2013)Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis., , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (9): 2119-2130 (2019)On Efficient Retiming of Fixed-Point Circuits.. IEEE Trans. Very Large Scale Integr. Syst., 24 (4): 1257-1265 (2016)Low Latency Scaling-Free Pipeline CORDIC Architecture Using Augmented Taylor Series., , and . iSES, page 312-315. IEEE, (2019)Analysis and Optimization of Product-Accumulation Section for Efficient Implementation of FIR Filters., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (10): 1701-1713 (2016)High-Speed RS(255, 239) Decoder Based on LCC Decoding., , and . CSSP, 30 (6): 1643-1669 (2011)Hardware-Efficient Realization of Prime-Length DCT Based on Distributed Arithmetic., , and . IEEE Trans. Computers, 62 (6): 1170-1178 (2013)Scalable Serial-parallel Multiplier over GF(2m) by Hierarchical Pre-reduction and Input Decomposition., and . ISCAS, page 2910-2913. IEEE, (2009)