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Disambiguation of "Lee, Chiou-Yng"

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Scalable Serial-parallel Multiplier over GF(2m) by Hierarchical Pre-reduction and Input Decomposition.

, and . ISCAS, page 2910-2913. IEEE, (2009)

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Min-Ching Chiou

Irmgard Chiout

Jakob Yngvason

Emmanouil Chiou

Derek Chiou

 

Other publications of authors with the same name

A Linear Time Pessimistic Diagnosis Algorithm for Hypermesh Multiprocessor Systems under the PMC Model., , , , and . IEEE Trans. Computers, 63 (12): 2894-2904 (2014)Bit-Parallel Systolic Multipliers for GF(2m) Fields Defined by All-One and Equally Spaced Polynomials., , and . IEEE Trans. Computers, 50 (5): 385-393 (2001)Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space Complexity., and . FPGA, page 187. ACM, (2019)Low-Complexity Systolic Multiplier for GF(2m) using Toeplitz Matrix-Vector Product Method., , and . ISCAS, page 1-5. IEEE, (2019)Low-complexity bit-parallel systolic multipliers over GF(2m).. Integr., 41 (1): 106-112 (2008)Concurrent Error Detection in Multiplexer-Based Multipliers for Normal Basis of GF(2m) Using Double Parity Prediction Scheme., , and . J. Signal Process. Syst., 58 (2): 233-246 (2010)Concurrent Error Detection in a Polynomial Basis Multiplier over GF(2m)., , and . J. Electron. Test., 22 (2): 143-150 (2006)Concurrent error detection in semi-systolic dual basis multiplier over GF(2m) using self-checking alternating logic., , , , and . IET Circuits Devices Syst., 4 (5): 382-391 (2010)Efficient Digit-Serial KA-Based Multiplier Over Binary Extension Fields Using Block Recombination Approach., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (8): 2044-2051 (2015)Dual-Basis Superserial Multipliers for Secure Applications and Lightweight Cryptographic Architectures., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (2): 125-129 (2014)