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Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology.

S. Clerc, F. Abouzeid, D. Patel, J. Daveau, C. Bottoni, L. Ciampolini, F. Giner, D. Meyer, R. Wilson, P. Roche, S. Naudet, A. Virazel, A. Bosio, and P. Girard. ISQED, page 366-370. IEEE, (2015)

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Arnaud Mende

Arnaud Moris

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A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction.N. Badereddine, Z. Wang, P. Girard, K. Chakrabarty, A. Virazel, S. Pravossoudovitch, and C. Landrault. J. Electron. Test., 24 (4): 353-364 (2008)An efficient hybrid power modeling approach for accurate gate-level power estimation.A. Nocua, A. Virazel, A. Bosio, P. Girard, and C. Chevalier. ICM, page 17-20. IEEE, (2015)A Lightweight, Plug-and-Play and Autonomous JTAG Authentication IP for Secure Device Testing.S. Lapeyre, N. Valette, M. Merandat, M. Flottes, B. Rouzeyre, and A. Virazel. ETS, page 1-4. IEEE, (2022)Random Adjacent Sequences: An Efficient Solution for Logic BIST.R. David, P. Girard, C. Landrault, S. Pravossoudovitch, and A. Virazel. VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 413-424. Kluwer, (2001)Parity prediction synthesis for nano-electronic gate designs.D. Tran, A. Virazel, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, and H. Wunderlich. ITC, page 820. IEEE Computer Society, (2010)Approximate computing: Design & test for integrated circuits.A. Bosio, A. Virazel, P. Girard, and M. Barbareschi. LATS, page 1. IEEE, (2017)Low-power SRAMs power mode control logic: Failure analysis and test solutions.L. Zordan, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, and N. Badereddine. ITC, page 1-10. IEEE Computer Society, (2012)Impact of resistive-open defects on the heat current of TAS-MRAM architectures.J. Azevedo, A. Virazel, A. Bosio, L. Dilillo, P. Girard, A. Todri-Sanial, G. Prenat, J. Alvarez-Herault, and K. Mackay. DATE, page 532-537. IEEE, (2012)Failure Analysis and Test Solutions for Low-Power SRAMs.L. Zordan, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Todri, A. Virazel, and N. Badereddine. Asian Test Symposium, page 459-460. IEEE Computer Society, (2011)Towards digital circuit approximation by exploiting fault simulation.M. Traiola, A. Virazel, P. Girard, M. Barbareschi, and A. Bosio. EWDTS, page 1-7. IEEE Computer Society, (2017)

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Disambiguation of "Virazel, Arnaud"

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Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology.

Please choose a person to relate this publication to

Arnaud Mende

Arnaud Moris

Julien Arnaud

Arnaud Dewalque

Arnaud Casteigts

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Virazel, Arnaud"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology.

Please choose a person to relate this publication to

Arnaud Mende

Arnaud Moris

Julien Arnaud

Arnaud Dewalque

Arnaud Casteigts

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
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Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology.