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Random Adjacent Sequences: An Efficient Solution for Logic BIST., , , , и . VLSI-SOC, том 218 из IFIP Conference Proceedings, стр. 413-424. Kluwer, (2001)Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles., , , , и . VLSI-SoC, том 240 из IFIP, стр. 267-281. Springer, (2005)On hardware generation of random single input change test sequences., , , , и . ETW, стр. 117-123. IEEE Computer Society, (2001)Intra-Cell Defects Diagnosis., , , , , , и . J. Electron. Test., 30 (5): 541-555 (2014)A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction., , , , , , , , и . European Test Symposium, стр. 81-86. IEEE Computer Society, (2010)Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes., , , , , , и . European Test Symposium, стр. 132-137. IEEE Computer Society, (2010)Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation., , , , и . IEEE Trans. Very Large Scale Integr. Syst., 21 (5): 958-970 (2013)A Survey of Test and Reliability Solutions for Magnetic Random Access Memories., , , , , и . Proc. IEEE, 109 (2): 149-169 (2021)A Survey of Testing Techniques for Approximate Integrated Circuits., , , , и . Proc. IEEE, 108 (12): 2178-2194 (2020)Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test., , , , , и . J. Electron. Test., 21 (2): 169-179 (2005)