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A 28nm 36kb high speed 6T SRAM with source follower PMOS read and bit-line under-drive.

, , , , , и . ISCAS, стр. 2549-2552. IEEE, (2015)

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Nabil Al-Jou Jou

Shyh-Yuong Lee

Ren-Jye Shiue

Shyi-Ming Jou

Yuan-jeh Jou

 

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Digitally-controlled cell-based oscillator with multi-phase differential outputs., и . ASICON, стр. 610-613. IEEE, (2011)A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code., , и . ISCAS (5), стр. 293-296. IEEE, (2004)An IEEE 802.15.3c/802.11ad compliant SC/OFDM dual-mode baseband receiver for 60 GHz Band., , , , , , , , и . ISCAS, стр. 1006-1009. IEEE, (2014)A Parallel Event-Driven MOS Timing Simulator on Distributed-Memory Multiprocessors., , и . ISCAS, стр. 574-577. IEEE, (1995)A 40Gb/s All-Digital Adaptive Noise-Suppression Feed-Forward Filter and Adaptive Decision Feedback Equalizer with 40 parallelisms for 2-PAM Systems., , , , и . ISCAS, стр. 1-4. IEEE, (2018)10Gbps Decision Feedback Equalizer with Dynamic Lookahead Decision Loop., , и . ISCAS, стр. 1839-1842. IEEE, (2009)Sub-word and reduced-width Booth multipliers for DSP applications., , , , и . ISCAS (3), стр. 575-578. IEEE, (2002)A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists., , , , , , , , , и 2 other автор(ы). SoCC, стр. 455-462. IEEE, (2014)Gb/s prototyping of 60GHz indoor wireless SC/OFDM transmitter and receiver on FPGA demo system., , , , , , и . ICCE-TW, стр. 204-205. IEEE, (2015)A 50 Gb/s Adaptive ADFE with SNR Based Power Management for 2-PAM Systems., , и . VLSI-DAT, стр. 1-4. IEEE, (2019)