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Disambiguation of "Arakida, Hideho"

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Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques.

, , , , , , , , and . DAC, page 483-488. ACM Press, (1998)

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Comparing memory systems for chip multiprocessors., , , , , and . ISCA, page 358-368. ACM, (2007)A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 33 (11): 1772-1780 (1998)A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 46 (1): 32-41 (2011)Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques., , , , , , , , and . DAC, page 483-488. ACM Press, (1998)A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 41 (1): 54-62 (2006)A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme., , , , , , , , , and . CICC, page 495-498. IEEE, (1998)A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm., , , , , , , , , and 4 other author(s). ISSCC, page 326-327. IEEE, (2010)A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 35 (11): 1713-1721 (2000)A Single-Chip Low-Power Mpeg-4 Audiovisual Lsi Using Embedded Dram Technology., , , and . ICME, IEEE Computer Society, (2001)A Power, Performance Scalable Eight-Cores Media Processor for Mobile Multimedia Applications., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 44 (11): 2957-2965 (2009)