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A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors.

H. Amano, Y. Hasegawa, S. Abe, K. Ishikawa, S. Tsutsumi, S. Kurotaki, T. Nakamura, and T. Nishimura. FPL, page 1-6. IEEE, (2006)

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Noboru Hasegawa

Masahito Hasegawa

Yohei Harayama

Shuichi Hasegawa

Other publications of authors with the same name

Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor with Directly Interconnected PEs.M. Kato, Y. Hasegawa, and H. Amano. ERSA, page 215-221. CSREA Press, (2008)Overwrite Configuration Technique in Multicast Configuration Scheme for Dynamically Reconfigurable Processor Arrays.S. Tsutsumi, V. Tunbunheng, Y. Hasegawa, A. Parimala, T. Nakamura, T. Nishimura, and H. Amano. FPT, page 273-276. IEEE, (2007)Power reduction techniques for Dynamically Reconfigurable Processor Arrays.T. Nishimura, K. Hirai, Y. Saito, T. Nakamura, Y. Hasegawa, S. Tsutsumi, V. Tunbunheng, and H. Amano. FPL, page 305-310. IEEE, (2008)A Multi-User ACK-Aggregation Method for Large-Scale Reliable LoRaWAN Service.Y. Hasegawa, and K. Suzuki. ICC, page 1-7. IEEE, (2019)A Throughput Model of TCP-FSO/ADFR for Free-Space Optical Satellite Communications.Y. Hasegawa, T. Ito, Y. Ono, and M. Arikawa. GLOBECOM, page 1-6. IEEE, (2019)Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique.Y. Saito, T. Shirai, T. Nakamura, T. Nishimura, Y. Hasegawa, S. Tsutsumi, T. Kashima, M. Nakata, S. Takeda, K. Usami and 1 other author(s). FPT, page 329-332. IEEE, (2008)TCP throughput characteristics over 5G millimeterwave network in indoor train station.M. Okano, Y. Hasegawa, K. Kanai, B. Wei, and J. Katto. WCNC, page 1-6. IEEE, (2019)A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors.H. Amano, Y. Hasegawa, S. Abe, K. Ishikawa, S. Tsutsumi, S. Kurotaki, T. Nakamura, and T. Nishimura. FPL, page 1-6. IEEE, (2006)Flexible and automated operational control in SDN transport-base virtual router.M. Hayashitani, Y. Hasegawa, K. Suzuki, and Y. Mizukoshi. OFC, page 1-3. IEEE, (2014)Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor.N. Suzuki, S. Kurotaki, M. Suzuki, N. Kaneko, Y. Yamada, K. Deguchi, Y. Hasegawa, H. Amano, K. Anjo, M. Motomura and 3 other author(s). FCCM, page 328-329. IEEE Computer Society, (2004)

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Disambiguation of "Hasegawa, Yohei"

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A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors.

Please choose a person to relate this publication to

Noboru Hasegawa

Masahito Hasegawa

Yohei Harayama

Shuichi Hasegawa

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Hasegawa, Yohei"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors.

Please choose a person to relate this publication to

Noboru Hasegawa

Masahito Hasegawa

Yohei Harayama

Shuichi Hasegawa

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors.