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A reconfigurable PUF structure with dual working modes based on entropy separation model., , , , , , and . Microelectron. J., (2022)Balancing wrapper chains of SoC core based on best interchange decreasing., , and . SoC, page 1-4. IEEE, (2008)A dynamically reconfigurable entropy source circuit for high-throughput true random number generator., , , , , and . Microelectron. J., (March 2023)Jitter-Quantizing-Based TRNG Robust Against PVT Variations., , , , , , , and . IEEE Access, (2020)A Low Power-Consumption Triple-Node-Upset-Tolerant Latch Design., , , , , , , and . J. Electron. Test., 38 (1): 63-76 (2022)A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application., , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (2): 287-291 (2019)Design of True Random Number Generator Based on Multi-Stage Feedback Ring Oscillator., , , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (3): 1752-1756 (2022)High-Throughput Portable True Random Number Generator Based on Jitter-Latch Structure., , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (2): 741-750 (2021)An Output-Capacitorless Ultra-Low Power Low-Dropout Regulator., , , , , and . J. Circuits Syst. Comput., 26 (12): 1750193:1-1750193:11 (2017)A Pulse Shrinking-Based Test Solution for Prebond Through Silicon via in 3-D ICs., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (4): 755-766 (2019)