Author of the publication

Balancing wrapper chains of SoC core based on best interchange decreasing.

, , and . SoC, page 1-4. IEEE, (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

CPCA: An efficient wireless routing algorithm in WiNoC for cross path congestion awareness., , , , , and . Integr., (2019)Architecting a congestion pre-avoidance and load-balanced wireless network-on-chip., , and . J. Parallel Distributed Comput., (2022)A reconfigurable PUF structure with dual working modes based on entropy separation model., , , , , , and . Microelectron. J., (2022)Design of MNU-Resilient latches based on input-split C-elements., , , , , , and . Microelectron. J., (2021)Reliability analysis and comparison of ring-PUF based on probabilistic models., , , , , and . Microelectron. J., (February 2024)Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications., , , , , , , and . ISCAS, page 1-5. IEEE, (2020)Balancing wrapper chains of SoC core based on best interchange decreasing., , and . SoC, page 1-4. IEEE, (2008)A tree-recursive partitioned multicast mechanism for NoC-based deep neural network accelerator., , , and . Microelectron. J., (2024)A Pulse Shrinking-Based Test Solution for Prebond Through Silicon via in 3-D ICs., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (4): 755-766 (2019)LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 2938-2951 (2020)