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A novel yield aware multi-objective analog circuit optimization tool., , , , and . ISCAS, page 2652-2655. IEEE, (2015)Reliability assessment of CMOS differential cross-coupled LC oscillators and a novel on chip self-healing approach against aging phenomena., , and . Microelectron. Reliab., 54 (2): 397-403 (2014)Synthesis of clock trees for Sampled-Data Analog IC blocks., , , , , , , , , and . EWDTS, page 1-4. IEEE Computer Society, (2013)On Chip Reconfigurable CMOS Analog Circuit Design and Automation Against Aging Phenomena: Sense and React., , , , and . ACM Trans. Design Autom. Electr. Syst., 24 (4): 44:1-44:22 (2019)A lifetime-aware analog circuit sizing tool., , , , and . Integr., (2016)A Verifiable High Level Data Path Synthesis Framework., , , , and . DSD, page 397-404. IEEE Computer Society, (2012)High-Level verifiable data-path Synthesis for DSP systems., , , , and . SIU, page 1-4. IEEE, (2012)Semi-empirical aging model development via accelerated aging test., , , and . SMACD, page 1-4. IEEE, (2016)Image processing system using a programmable transform imager., , , , and . ICASSP (5), page 101-104. IEEE, (2005)Hierarchical Placement for Large-scale FPAA., , , and . FPL, page 421-426. IEEE, (2005)