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Disambiguation of "Xie, Jiafeng"

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Monocular Road Planar Parallax Estimation.

, , , , , , and . IEEE Trans. Image Process., (2023)

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Jiafeng Zhang

Jian Xie

Yangpei Xie

Qian Xie

Mingliang Xie

 

Other publications of authors with the same name

Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space Complexity., and . FPGA, page 187. ACM, (2019)Low-Complexity Systolic Multiplier for GF(2m) using Toeplitz Matrix-Vector Product Method., , and . ISCAS, page 1-5. IEEE, (2019)Low-latency area-delay-efficient systolic multiplier over GF(2m) for a wider class of trinomials using parallel register sharing., , and . ISCAS, page 89-92. IEEE, (2012)Reliable Inversion in GF(28) With Redundant Arithmetic for Secure Error Detection of Cryptographic Architectures., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (3): 696-704 (2018)Hardware Efficient Approach for Memoryless-Based Multiplication and Its Application to FIR Filter., and . J. Comput., 6 (11): 2376-2381 (2011)FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers Over $GF(2^m)$ and Their Applications in Trinomial Multipliers., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (2): 725-734 (2017)FPGA realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures., , and . Microelectron. J., 41 (6): 365-370 (2010)FEED: A Chinese Financial Event Extraction Dataset Constructed by Distant Supervision., , , , and . IJCKG, page 45-53. ACM, (2021)Ultra Low-Complexity Implementation of Binary Ring-LWE based Post-Quantum Cryptography on FPGA Platform., , and . FPGA, page 156. ACM, (2022)Work-in-Progress: High-Performance Systolic Hardware Accelerator for RBLWE-based Post-Quantum Cryptography., , , and . CODES+ISSS, page 5-6. IEEE, (2022)