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Disambiguation of "Mashiko, Koichiro"

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Test Pattern Considerations for Fault Tolerant High Density DRAM.

, , , , , and . ITC, page 451-455. IEEE Computer Society, (1985)

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Koichiro Agata

Koichiro Iwata

 

Other publications of authors with the same name

A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm., , , , , , , , , and 4 other author(s). IEICE Trans. Electron., 90-C (6): 1181-1188 (2007)Leading-zero anticipatory logic for high-speed floating point addition., , , , , and . IEEE J. Solid State Circuits, 31 (8): 1157-1164 (1996)A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology., , , , , and . IEEE J. Solid State Circuits, 35 (5): 751-756 (2000)A fully compensated active pull-down ECL circuit with self-adjusting driving capability., , , and . IEEE J. Solid State Circuits, 31 (1): 46-53 (1996)Comments on "Leading-zero anticipatory logic for high-speed floating point addition" with reply., , , , , , and . IEEE J. Solid State Circuits, 32 (2): 292 (1997)Test Pattern Considerations for Fault Tolerant High Density DRAM., , , , , and . ITC, page 451-455. IEEE Computer Society, (1985)Complex Bandpass DeltaSigmaAD Modulator Architecture without I, Q-Path Crossing Layout., , , , , , , , , and 5 other author(s). IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (4): 908-915 (2006)An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture., , , , , and . IEEE J. Solid State Circuits, 31 (6): 773-783 (1996)Authors Reply., , , , and . IEEE J. Solid State Circuits, 32 (2): 293 (1997)A voltage compensated series-gate bipolar circuit operating at sub-2 V., , , , and . IEEE J. Solid State Circuits, 29 (10): 1200-1205 (October 1994)