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Disambiguation of "Yamada, Michihiro"

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Test Pattern Considerations for Fault Tolerant High Density DRAM.

, , , , , and . ITC, page 451-455. IEEE Computer Society, (1985)

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Chisaburo Yamada

Michihiro Saito

Osamu Yamada

Hitoshi Yamada

Keiichi Yamada

 

Other publications of authors with the same name

Decision Tree Analysis on Environmental Factors of Insider Threats., , and . HCI (30), volume 714 of Communications in Computer and Information Science, page 658-662. Springer, (2017)Design methodology of embedded DRAM with virtual-socket architecture., , , , , , , and . IEEE J. Solid State Circuits, 36 (1): 46-54 (2001)Mathematical Model to Estimate Loss by Cyber Incident in Japan., , , and . ICISSP, page 353-360. SciTePress, (2019)An Address Maskable Parallel Testing for Ultra High Density DRAMs., , , and . ITC, page 556-563. IEEE Computer Society, (1991)A 5.3-GB/s embedded SDRAM core with slight-boost scheme., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 34 (5): 661-669 (1999)High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's., , , , , and . IEEE J. Solid State Circuits, 32 (3): 477-482 (1997)Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 34 (4): 494-501 (1999)How Much is Risk Increased by Sharing Credential in Group?, , and . STM, volume 10547 of Lecture Notes in Computer Science, page 103-117. Springer, (2017)Evaluation and Development of Onomatopoeia CAPTCHAs., , , and . PST, page 1-2. IEEE Computer Society, (2018)Test Pattern Considerations for Fault Tolerant High Density DRAM., , , , , and . ITC, page 451-455. IEEE Computer Society, (1985)