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Disambiguation of "Chacon-Rodriguez, Alfonso"

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Design of an IDM-based determinant computing unit for a 130nm low power CMOS ASIC acoustic localization processor.

, , , and . LASCAS, page 1-4. IEEE, (2015)

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Sabrina Alfonso

Alfonso Ortega

Alfonso Lampen

Alfonso Almendral

Alfonso Verdú

 

Other publications of authors with the same name

Design of an IDM-based determinant computing unit for a 130nm low power CMOS ASIC acoustic localization processor., , , and . LASCAS, page 1-4. IEEE, (2015)Triggers for Irrigation Decision-Making in Greenhouse Horticulture using Internet of Things., and . ISCAS, page 1-4. IEEE, (2020)PlasticNet+: Extending Multi-FPGA Interconnect Architecture via Gigabit Transceivers., , , , and . ISCAS, page 1-5. IEEE, (2021)Prototyping a Biologically Plausible Neuron Model on a Heterogeneous CPU-FPGA Board., , , , , , and . LASCAS, page 5-8. IEEE, (2019)A comparison of low power architectures for digital delay measurement., , , and . ISVLSI, page 498-499. IEEE Computer Society, (2007)SoC-FPGA Implementation of a Temperature-Dependent Parameters Estimator for Photovoltaic Generators., , , , and . LASCAS, page 1-4. IEEE, (2020)An Adaptive Cross-Correlation Derivative Algorithm for Ultra-Low Power Time Delay Measurement., , , and . ISCAS, page 4016-4019. IEEE, (2007)A Low-Power Integrated Circuit for Interaural Time Delay Estimation Without Delay Lines., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 56-II (7): 575-579 (2009)RISC-V based sound classifier intended for acoustic surveillance in protected natural environments., , and . LASCAS, page 1-4. IEEE, (2017)An asymmetrical bulk-modified composite MOS transistor with enhanced linearity., , , , and . LASCAS, page 49-52. IEEE, (2019)