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Robust testability of primitive faults using test points.

, and . ITC, page 260-268. IEEE Computer Society, (1999)

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Structural Simplification and Decomposition of Asynchronous Sequential Circuits., , and . IEEE Trans. Computers, 18 (9): 830-838 (1969)Test Generation In Lamp2: System Overview., , , and . ITC, page 45-48. IEEE Computer Society, (1985)Delay Testing with Clock Control: An Alternative to Enhanced Scan., and . ITC, page 454-462. IEEE Computer Society, (1997)Test Generation Algorithms for Computer Hardware Description Languages., and . IEEE Trans. Computers, 31 (7): 577-588 (1982)Design of Asynchronous Circuits Assuming Unbounded Gate Delays., , and . IEEE Trans. Computers, 18 (12): 1110-1120 (1969)SCRIPT: a critical path tracing algorithm for synchronous sequential circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (6): 738-747 (1991)Symbolic Test Generation for Hierarchically Modeled Digital Systems., and . ITC, page 461-469. IEEE Computer Society, (1989)Delay-Verifiability of Combinational Circuits Based on Primitive Faults., and . ICCD, page 86-90. IEEE Computer Society, (1994)Identification of primitive faults in combinational and sequentialcircuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (12): 1426-1442 (2001)Acceleration of trace-based fault simulation of combinational circuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (9): 1413-1419 (1993)