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A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators.

Y. Lee, A. Waterman, R. Avizienis, H. Cook, C. Sun, V. Stojanovic, and K. Asanovic. ESSCIRC, page 199-202. IEEE, (2014)

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FASED: FPGA-Accelerated Simulation and Evaluation of DRAM.D. Biancolin, S. Karandikar, D. Kim, J. Koenig, A. Waterman, J. Bachrach, and K. Asanovic. FPGA, page 330-339. ACM, (2019)Optimizing Matrix Multiply Using PHiPAC: A Portable, High-Performance, ANSI C Coding Methodology.J. Bilmes, K. Asanovic, C. Chin, and J. Demmel. International Conference on Supercomputing, page 340-347. ACM, (1997)An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET.C. Schmidt, J. Wright, Z. Wang, E. Chang, A. Ou, W. Bae, S. Huang, V. Milovanovic, A. Flynn, B. Richards and 3 other author(s). IEEE J. Solid State Circuits, 57 (1): 140-152 (2022)Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors.R. Jevtic, H. Le, M. Blagojevic, S. Bailey, K. Asanovic, E. Alon, and B. Nikolic. IEEE Trans. Very Large Scale Integr. Syst., 23 (4): 723-730 (2015)Energy-aware lossless data compression.K. Barr, and K. Asanovic. ACM Trans. Comput. Syst., 24 (3): 250-291 (2006)Building Open Trusted Execution Environments.D. Kohlbrenner, S. Shinde, D. Lee, K. Asanovic, and D. Song. IEEE Secur. Priv., 18 (5): 47-56 (2020)The GAP Benchmark Suite.S. Beamer, K. Asanovic, and D. Patterson. CoRR, (2015)A 16mm2 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET.A. Gonzalez, J. Zhao, B. Korpan, H. Genc, C. Schmidt, J. Wright, A. Biswas, A. Amid, F. Sheikh, A. Sorokin and 9 other author(s). ESSCIRC, page 259-262. IEEE, (2021)CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems.S. Karandikar, A. Udipi, J. Choi, J. Whangbo, J. Zhao, S. Kanev, E. Lim, J. Alakuijala, V. Madduri, Y. Shao and 3 other author(s). ISCA, page 39:1-39:17. ACM, (2023)Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors.M. Zhang, and K. Asanovic. ISCA, page 336-345. IEEE Computer Society, (2005)

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Disambiguation of "Asanovic, Krste"

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A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators.

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Disambiguation of "Asanovic, Krste"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators.

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A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators.